TY - BOOK
AU - Bellido, Manuel J.
AU - Chico, Jorge Juan
AU - Valencia, Manuel
AU - Juan, Jorge
TI - Logic-timing simulation and the degradation delay model
PB - Imperial College Press
SN - 1860945899
SN - 9781860945892
KW - Timing circuits
KW - Integrated circuits Very large scale integration
KW - Metal oxide semiconductors, Complementary
KW - MOS-FET
KW - VLSI
KW - Zeitabhängigkeit
PY - c 2006
N2 - Literaturverz. S. 251 - 263
CY - London
UR - http://slubdd.de/katalog?TN_libero_mab2
ER -
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