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  7. Höppner, Sebastian [Author] ; Schüffny, René [Degree supervisor]; Rückert, Ulrich [Degree supervisor]

    Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

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    Dresden: Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden; Dresden: Technische Universität Dresden, 2016

  8. Dammak Masmoudi, Bouthaina [Author] ; Valenciennes [Contributor]; École nationale d'ingénieurs de Sfax (Tunisie) [Contributor]; Niar, Smaïl [Contributor]; Abid, Mohamed [Contributor]; Benmansour, Rachid [Contributor]; Baklouti Kammoun, Mouna [Contributor]

    Optimisation des performances et de la complexité dans les architectures multiprocesseurs hétérogènes sur puce ; Performance and complexity optimization in heterogeneous multiprocessors system on chip

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    theses.fr, 2015-11-06

  9. Serrano-Cases, Alejandro [Author]; Reina, Juan M. [Author]; Abella, Jaume [Author]; Mezzetti, Enrico [Author]; Cazorla, Francisco J. [Author] ; Alejandro Serrano-Cases and Juan M. Reina and Jaume Abella and Enrico Mezzetti and Francisco J. Cazorla [Contributor]

    Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC

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    Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2021

  15. Hölzenspies, Philip K. F. [Author]; Kuper, Jan [Author]; Smit, Gerard J. M. [Author]; Hurink, Johann [Author] ; Philip K. F. Hölzenspies and Jan Kuper and Gerard J. M. Smit and Johann Hurink [Contributor]

    Demonstration of Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)

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    Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2007