author = { Bellido, Manuel J. AND Chico, Jorge Juan AND Valencia, Manuel Juan, Jorge },

title = { Logic-timing simulation and the degradation delay model },

publisher = {Imperial College Press},

isbn = {1860945899},

isbn = {9781860945892},

keywords = { Timing circuits , Integrated circuits Very large scale integration , Metal oxide semiconductors, Complementary , MOS-FET , VLSI , Zeitabhängigkeit },

year = {c 2006},

abstract = {Literaturverz. S. 251 - 263},

address = { London },

url = { http://slubdd.de/katalog?TN_libero_mab2 }