%0 Book
%T Logic-timing simulation and the degradation delay model
%A Bellido, Manuel J.
%A Chico, Jorge Juan
%A Valencia, Manuel
%A Juan, Jorge
%I Imperial College Press
%@ 1860945899
%@ 9781860945892
%K Timing circuits
%K Integrated circuits Very large scale integration
%K Metal oxide semiconductors, Complementary
%K MOS-FET
%K VLSI
%K Zeitabhängigkeit
%D c 2006
%X Literaturverz. S. 251 - 263
%C Imperial College Press
%C London
%U http://slubdd.de/katalog?TN_libero_mab2
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