%0 Generic
%T Integrated Circuit Design: Degradation Delay Model Extension to CMOS Gates
%A Juan-Chico, Jorge
%A Bellido, Manuel J.
%A Ruiz-de-Clavijo, Paulino
%A Acosta, Antonio J.
%A Valencia, Manuel
%I Springer Berlin Heidelberg
%@ 0302-9743
%D 2000
%C Springer Berlin Heidelberg
%U http://slubdd.de/katalog?TN_libero_mab2
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