TY - GEN
AU - Juan-Chico, Jorge
AU - Bellido, Manuel J.
AU - Ruiz-de-Clavijo, Paulino
AU - Acosta, Antonio J.
AU - Valencia, Manuel
TI - Integrated Circuit Design: Degradation Delay Model Extension to CMOS Gates
PB - Springer Berlin Heidelberg
SN - 0302-9743
PY - 2000
UR - http://slubdd.de/katalog?TN_libero_mab2
ER -
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