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Golze, Ulrich [Author] ; Blinzer, Peter [Other]

Der RISC-Prozessor TOOBSIE : Hintergrundband zum Buch "VLSI-Entwurf eines RISC-Prozessors" für den Entwurfsspezialisten

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Braunschweig [u.a.]: Vieweg, 1995

Published in: Vieweg-Informatik
Golze, Ulrich [Author]

VLSI chip design with the hardware description language VERILOG : an introduction based on a large RISC processor design

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Berlin; Heidelberg [u.a.]: Springer, 1996
Golze, Ulrich [Author] ; Blinzer, Peter [Other]

VLSI-Entwurf eines RISC-Prozessors : eine Einführung in das Design grosser Chips und die Hardware-Beschreibungssprache VERILOG HDL

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Braunschweig; Wiesbaden: Vieweg, 1995

Published in: Lehrbuch Informatik
Gonçalves Romero, Jorge Humberto [Author]

Entwurf einer zellularen flexiblen Rechnerarchitektur auf Transputerbasis für die Schaltungssimulation

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Düsseldorf: VDI-Verl., 1989

Published in: Verein Deutscher Ingenieure: Fortschrittberichte VDI / 9 ; 88
Furber, Stephen B. [Author]; Furber, Stephen Bo [Author]

VLSI RISC architecture and organization

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New York [u.a.]: Dekker, 1989

Published in: Electrical engineering and electronics ; 5600
Patterson; Sequin

A VLSI RISC

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Institute of Electrical and Electronics Engineers (IEEE), 1982

Published in: Computer
Lazzerini, B.

Effective VLSI processor architectures for HLL computers: the RISC approach

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Institute of Electrical and Electronics Engineers (IEEE), 1989

Published in: IEEE Micro
Patterson, David A.; Garrison, Phil; Hill, Mark; Lioupis, Dimitris; Nyberg, Chris; Sippel, Tim; Dyke, Korbin Van

Architecture of a VLSI instruction cache for a RISC

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Association for Computing Machinery (ACM), 1983

Published in: ACM SIGARCH Computer Architecture News
Kaneko, K.; Okamoto, T.; Nakajima, M.; Nakakura, Y.; Gokita, S.; Nishikawa, J.; Tanikawa, Y.; Kadota, H.

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

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Institute of Electrical and Electronics Engineers (IEEE), 1989

Published in: IEEE Journal of Solid-State Circuits
Lee, D.D.; Kong, S.I.; Hill, M.D.; Taylor, G.S.; Hodges, D.A.; Katz, R.H.; Patterson, D.A.

A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing

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Institute of Electrical and Electronics Engineers (IEEE), 1989

Published in: IEEE Journal of Solid-State Circuits

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Der RISC-Prozessor TOOBSIE : Hintergrundband zum Buch "VLSI-Entwurf eines RISC-Prozessors" für den Entwurfsspezialisten

Bookmarks

VLSI chip design with the hardware description language VERILOG : an introduction based on a large RISC processor design

Bookmarks

VLSI-Entwurf eines RISC-Prozessors : eine Einführung in das Design grosser Chips und die Hardware-Beschreibungssprache VERILOG HDL

Bookmarks

Entwurf einer zellularen flexiblen Rechnerarchitektur auf Transputerbasis für die Schaltungssimulation

Bookmarks

VLSI RISC architecture and organization

Bookmarks

A VLSI RISC

Access

Bookmarks

Effective VLSI processor architectures for HLL computers: the RISC approach

Access

Bookmarks

Architecture of a VLSI instruction cache for a RISC

Access

Bookmarks

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

Access

Bookmarks

A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing

Access

Bookmarks

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