• Medientyp: E-Artikel
• Titel: An Efficient Digital Background Control for Hybrid Transformer-Based Receivers
• Beteiligte: Castellano, Gerardo; Montanari, Daniele; De Caro, Davide; Manstretta, Danilo; Strollo, Antonio Giuseppe Maria
• Erschienen: IEEE, 2017
• Sprache: Englisch
• DOI: 10.1109/TCSI.2017.2759097
• ISSN: 1549-8328
• Schlagwörter: Impedance ; Receivers ; Antennas ; Ports (Computers) ; Algorithm design and analysis ; Windings ; Digital control ; 3G ; automated tuning ; duplexers ; FDD ; full-duplex ; modulated signal ; hybrid transformer ; self-interference cancellation ; SAW-less
• Zusammenfassung: The design and hardware implementation of a digital control system tailored to a hybrid transformer-based duplexer is proposed. Working at Nyquist sampling frequency, it finds the optimal transmit-receive isolation in about 150 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> even when modulated signals with high PAPR (16-QAM) are transmitted. A simple tracking algorithm, operating in background, preserves this condition over time. Uninterrupted system operation can be guaranteed through an auxiliary receiver with sub-mW power dissipation, minimizing the overhead of the entire control system. The algorithms are implemented on FPGA to carry out the experimental validation of the full hardware implementation. Moreover, the hardware overhead of the digital control algorithm is analyzed, synthesizing the digital circuit in 40-nm CMOS technology.
• Beschreibung: The design and hardware implementation of a digital control system tailored to a hybrid transformer-based duplexer is proposed. Working at Nyquist sampling frequency, it finds the optimal transmit-receive isolation in about 150 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> even when modulated signals with high PAPR (16-QAM) are transmitted. A simple tracking algorithm, operating in background, preserves this condition over time. Uninterrupted system operation can be guaranteed through an auxiliary receiver with sub-mW power dissipation, minimizing the overhead of the entire control system. The algorithms are implemented on FPGA to carry out the experimental validation of the full hardware implementation. Moreover, the hardware overhead of the digital control algorithm is analyzed, synthesizing the digital circuit in 40-nm CMOS technology.