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  2. Graham, Ian [Author] ; King, Tim [Other]; Graham-King [Other]

    The transputer handbook - [1. publ.]

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    New York [u.a.]: Prentice Hall, 1990

  12. Eberle, Hans [Author]

    Architektur moderner RISC-Mikroprozessoren

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    ETH, Eidgenössische Technische Hochschule Zürich, Departement Informatik, Institut für Computersysteme, 1997-06

    Published in: Technical report / Eidgenössische Technische Hochschule Zürich, Departement Informatik, 269

  13. Flatt, H. [Author]; Tarnowsky, A. [Author]; Blume, Holger [Author]; Pirsch, Peter [Author]

    Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur [Hardware mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture] - [published Version]

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    Göttingen : Copernicus GmbH, 2010

    Published in: Advances in Radio Science 8 (2010)

  15. Barchi, Francesco [Author]; Pasini, Giacomo [Author]; Parisi, Emanuele [Author]; Tagliavini, Giuseppe [Author]; Bartolini, Andrea [Author]; Acquaviva, Andrea [Author] ; Francesco Barchi and Giacomo Pasini and Emanuele Parisi and Giuseppe Tagliavini and Andrea Bartolini and Andrea Acquaviva [Contributor]

    RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper)

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    Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2023

  18. Bahr, Andreas [Author]; Schneider, Matthias [Author]; Francis, Maria Avitha [Author]; Lehmann, Hendrik M. [Author]; Barg, Igor [Author]; Buschhoff, Anna-Sophia [Author]; Wulff, Peer [Author]; Strunskus, Thomas [Author]; Faupel, Franz [Author]

    Epileptic seizure detection on an ultra-low-power embedded risc-v processor using a convolutional neural network

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    2021

    Published in: Biosensors ; 11(2021), 7, Artikel-ID 203, Seite 1-18

  19. Dörflinger, Alexander [Author]; Guan, Yejun [Author]; Michalik, Sören [Author]; Michalik, Sönke [Author]; Naghmouchi, Jamin [Author]; Michalik, Harald [Author]

    ECC Memory for Fault Tolerant RISC-V Processors

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    Springer, 2020

    Published in: Brinkmann A., Karl W., Lankes S., Tomforde S., Pionteck T., Trinitis C. (eds), Architecture of Computing Systems – ARCS 2020. ARCS 2020. Lecture Notes in Computer Science, vol 12155, Page 44 - 55, Springer, Cham. https://doi.org/10.1007/978-3-030-52794-5_4 -- Lecture Notes in Computer Science -- Lect. Notes Comput. Sci. -- 0302-9743

  20. Kamaleldin, Ahmed [Author]; Göhringer, Diana [Author]

    AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

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    NY: IEEE - Institute of Electrical and Electronics Engineers, New York, [2024]

    Published in: IEEE Access ; 10 (2022), Seite 43895-43913