Media type: Book; Thesis Title: Integrierte Placement- und Timing-Optimierung beim physikalischen Layout von nicht-hierarchischen Designs hochintegrierter Logikchips Contributor: Schülter, Dieta [Author] Published: 2002 Extent: II, 121 S.; Ill., graph. Darst Language: German RVK notation: ZN 4904 : Schaltungsentwurf Keywords: VLSI > Chip > Logiksynthese > Timingsimulation > Platzierung Origination: University thesis: Bonn, Univ., Diss., 2002 Footnote:
Departmental Library DrePunct – stack Shelf-mark: 2007 4 001320 Item ID: 31616289 Status: Loanable, place order > Ordering possible ‒ please log in Delivery expected: 1 - 2 days after order