Media type: Book Title: Verification by error modeling : using testing techniques in hardware verification Contributor: Radecka, Katarzyna [Author]; Zilic, Zeljko [Author] Published: Boston, Mass. [u.a.]: Kluwer, 2003 Published in: Frontiers in electronic testing Extent: XIV, 216 S.; graph. Darst Language: Not determined ISBN: 1402076525 RVK notation: ZN 4030 : Prüfverfahren in der Technischen Elektronik allgemein; Fehlererkennungsschaltungen; Test elektronischer Schaltungen und Bauelemente Keywords: VLSI > Hardwareverifikation > Schaltungsentwurf Origination: Footnote:
Departmental Library DrePunct – stack Shelf-mark: 2005 8 043919 Item ID: 31461517 Status: Loanable, place order > Ordering possible ‒ please log in Delivery expected: 1 - 2 days after order