> Details

Chen, Hualun [Author]; Xu, Zhaozhao [Author]; Xiong, Wei [Author]; Zhang, Jian [Author]; Xu, Xiaojun [Author]; Wang, Hui [Author]; Dang, Yang [Author]; Wang, Jinfeng [Author]; Song, Wan [Author]; Tian, Tian [Author]; Liu, Donghua [Author]; Qian, Wensheng [Author]; Kong, Weiran [Author]

Fabrication and Optimization of Aggressively Scaled Dual-Bit/Cell Split-Gate Floating-Gate Flash Memory Cell in 55-Nm Node Technology

Reference
management

Bookmarks

Remove from
bookmarks

Share this on Whatsapp

Close

Bookmarks



You can manage bookmarks using lists, please log in to your user account for this.
  • Media type: E-Book
  • Title: Fabrication and Optimization of Aggressively Scaled Dual-Bit/Cell Split-Gate Floating-Gate Flash Memory Cell in 55-Nm Node Technology
  • Contributor: Chen, Hualun [VerfasserIn]; Xu, Zhaozhao [VerfasserIn]; Xiong, Wei [VerfasserIn]; Zhang, Jian [VerfasserIn]; Xu, Xiaojun [VerfasserIn]; Wang, Hui [VerfasserIn]; Dang, Yang [VerfasserIn]; Wang, Jinfeng [VerfasserIn]; Song, Wan [VerfasserIn]; Tian, Tian [VerfasserIn]; Liu, Donghua [VerfasserIn]; Qian, Wensheng [VerfasserIn]; Kong, Weiran [VerfasserIn]
  • imprint: [S.l.]: SSRN, [2022]
  • Extent: 1 Online-Ressource (6 p)
  • Language: English
  • DOI: 10.2139/ssrn.4031131
  • Identifier:
  • Origination:
  • Footnote:
  • Description: An aggressively scaled triple self-aligned split-gate floating-gate (FG) NOR-type dual-bit/cell (NORD) flash cell with a common select-gate (SG) was fabricated at 55-nm node technology. Both FG- and SG-length, for the first time, were scaled down to sub-80 nm and sub-60 nm in our NORD flash, respectively. In this paper, performance of aggressively scaled cells were fully characterized by measurements. Firstly, the cell's characteristics were presented by discussing FG- and SG-transistor’s drain-induced barrier lowering (DIBL) effects and SG-FG coupling effect. It was experimentally revealed that excellent immunity of DIBL effect was still obtained in this highly scaled SG-transistor due to the fully isolated SG-channel. Then, optimization from process for FG-transistor has been discussed. It was shown that the properties of subthreshold region of FG-transistor has been improved by introducing dual pockets for half isolated FG-channel. Thirdly, reading biases were also optimized to expand the window of read currents. Finally, a novel cell structure, which is compatible with 55-nm node CMOS technology, was also proposed to further improve the aggressively length-scaled NORD flash cell without sacrificing bit-area
  • Access State: Open Access