• Media type: E-Article
  • Title: Three-dimensional MoS2 nanosheet structures: CVD synthesis, characterization, and electrical properties
  • Contributor: Mathew, Sobin [VerfasserIn]; Reiprich, Johannes [VerfasserIn]; Narasimha, Shilpashree [VerfasserIn]; Abedin, Saadman [VerfasserIn]; Kurtash, Vladislav [VerfasserIn]; Thiele, Sebastian [VerfasserIn]; Hähnlein, Bernd [VerfasserIn]; Scheler, Theresa [VerfasserIn]; Flock, Dominik [VerfasserIn]; Jacobs, Heiko O. [VerfasserIn]; Pezoldt, Jörg [VerfasserIn]
  • imprint: 2023
  • Published in: Crystals ; 13(2023), 3, Artikel-ID 448, Seite 1-14
  • Language: English
  • DOI: 10.3390/cryst13030448
  • ISSN: 2073-4352
  • Identifier:
  • Origination:
  • Footnote:
  • Description: The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS2 nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N2 gas flow during the deposition process. The distinctive signals of MoS2 were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material’s crystallinity and its 2H-MoS2 nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS2 structures and their growth mechanisms. The strain energy produced by the compression between MoS2 islands is assumed to primarily drive the formation of vertical MoS2 nanosheets. In addition, vertical MoS2 structures that emerge from micro fissures (cracks) on individual MoS2 islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm2 V^-1 s^-1 and an estimated carrier concentration of 4.5 × 10^12 cm^-2. Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified.
  • Access State: Open Access