• Media type: Doctoral Thesis; E-Book; Electronic Thesis
  • Title: Timing Analysable Synchronisation Techniques for Parallel Programs on Embedded Multi-Cores
  • Contributor: Gerdes, Mike [Author]
  • imprint: Augsburg University Publication Server (OPUS), 2013-10-07
  • Language: English
  • Keywords: Eingebettetes System ; Mehrkernprozessor ; Parallelisierung ; Synchronisierung ; Hartes Echtzeitsystem
  • Origination:
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  • Description: The thesis on hand provides hardware-software co-design of timing analysable synchronisation techniques in embedded shared-memory multi-core processors. In hardware, an augmented memory controller including the logic to support consistent and atomic Read-Modify-Write (RMW) primitives for a predictable shared-memory multi-core processor has been developed. The techniques introduced with the augmented memory controller are also applicable to further (future) shared-memory multi-core platforms. On top of these RMW primitives, timing analysable software synchronisation techniques are provided. On the one hand, hard real-time (HRT) capable, worst-case efficient, lock-based synchronisation techniques employing busy-waiting (spinning) and blocking (suspending) are introduced. On the other hand, worst-case efficient barrier implementations for progress coordination of HRT threads are presented. The implemented hardware and software techniques are analysed in detail with an open-source static worst-case execution time (WCET) analysis tool, which supports the analysis of multithreaded parallel programs on shared-memory multi-cores. The static timing analysis includes worst-case memory latencies for the concurrent access of threads to a shared global memory, and allows for analysing multithreaded programs by introducing worst-case waiting times at synchronisation points. Furthermore, two benchmarking parallel programs, a parallel matrix multiplication and an Integer Fast Fourier Transformation, have been implemented and analysed using the proposed synchronisation techniques. The analyses have shown that busy-waiting spin locks are preferable over locking techniques with suspension for multithreaded parallel programs on shared-memory multi-core processors. Also, the static timing analyses indicate that pessimism in the WCET estimates could be further reduced by providing a technique that prioritises frequent normal load and store operations over infrequent RMW operations on synchronisation variables. The optimisation ...
  • Access State: Open Access