Park, S. D.;
Park, C.;
Gilmer, D. C.;
Park, H. K.;
Kang, C. Y.;
Lim, K. Y.;
Burham, C.;
Barnett, J.;
Kirsch, P. D.;
Tseng, H. H.;
Jammy, R.;
Yeom, G. Y.
Bulk and Interface effects on voltage linearity of ZrO2–SiO2 multilayered metal-insulator-metal capacitors for analog mixed-signal applications
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Media type:
E-Article
Title:
Bulk and Interface effects on voltage linearity of ZrO2–SiO2 multilayered metal-insulator-metal capacitors for analog mixed-signal applications
Contributor:
Park, S. D.;
Park, C.;
Gilmer, D. C.;
Park, H. K.;
Kang, C. Y.;
Lim, K. Y.;
Burham, C.;
Barnett, J.;
Kirsch, P. D.;
Tseng, H. H.;
Jammy, R.;
Yeom, G. Y.
Description:
<jats:p>Quadratic voltage coefficient of capacitance (VCC) for ZrO2–SiO2 multilayered dielectric metal-insulator-metal capacitors depends strongly on the stacking sequence of the layered dielectrics. The quadratic VCC of an optimized SiO2/ZrO2/SiO2 stack and ZrO2/SiO2/ZrO2 stack were +42 and −1094 ppm/V2, respectively, despite the same total SiO2 and ZrO2 dielectric thickness in the stack. The observed difference in quadratic VCC depending on dielectric stacking sequence is explained by taking into account both the interface and bulk dielectric responses to the applied voltage.</jats:p>