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Ranjan, Rajeev; Ponce, Pablo Mendoza; Hellweg, Wolf Lukas; Kyrmanidis, Alexandros; Saleh, Lait Abu; Schroeder, Dietmar; Krautschneider, Wolfgang H.

Integrated Circuit with Memristor Emulator Array and Neuron Circuits for Biologically Inspired Neuromorphic Pattern Recognition

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  • Media type: E-Article
  • Title: Integrated Circuit with Memristor Emulator Array and Neuron Circuits for Biologically Inspired Neuromorphic Pattern Recognition
  • Contributor: Ranjan, Rajeev; Ponce, Pablo Mendoza; Hellweg, Wolf Lukas; Kyrmanidis, Alexandros; Saleh, Lait Abu; Schroeder, Dietmar; Krautschneider, Wolfgang H.
  • imprint: World Scientific Pub Co Pte Lt, 2017
  • Published in: Journal of Circuits, Systems and Computers
  • Language: English
  • DOI: 10.1142/s0218126617501833
  • ISSN: 0218-1266; 1793-6454
  • Origination:
  • Footnote:
  • Description: <jats:p> This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate &amp; fire (I &amp; F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88[Formula: see text]ns to 4.99[Formula: see text][Formula: see text]s (200[Formula: see text]k[Formula: see text] to 204.8[Formula: see text]M[Formula: see text]) and other four having conductance ranging from 195[Formula: see text]ns to 190[Formula: see text][Formula: see text]s (5.2[Formula: see text]k[Formula: see text] to 5.12[Formula: see text]M[Formula: see text]). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I &amp; F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I &amp; F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350[Formula: see text]nm process. </jats:p>