(Invited) Nickel and Nickel-Platinum Silicide for BiCMOS Devices

Media type: E-Article
Title: (Invited) Nickel and Nickel-Platinum Silicide for BiCMOS Devices
Contributor: Wolansky, Dirk; Blaschke, Jean-Paul; Drews, Jürgen; Grabolla, Thomas; Heinemann, Bernd; Lenke, Thomas; Rücker, Holger; Schubert, Markus Andreas; Schulze, Sebastian; Stoll, Heinz-Peter; Zöllner, Marvin; Richter, Uwe; Deyo, Dan
imprint: The Electrochemical Society, 2020
Published in: ECS Meeting Abstracts
Language: Not determined
DOI: 10.1149/ma2020-02241749mtgabs
ISSN: 2151-2043
Keywords: General Medicine
Origination:
Footnote:
Description: <jats:p> Recently, the world’s fastest SiGe-HBT was presented by IHP researchers [1], which applies low ohmic nickel silicide (NiSi). Among other measures, this feature contributed to speed improvements. On the other hand, the integration of low-ohmic NiSi creates the risk for NiSi defects which could result in increased MOSFET leakage currents. The goal of this contribution is to find out from several two-step silicidations of Ni or NiPt layers a suitable process for a BiCMOS technology which enables low silicide R<jats:sub>S</jats:sub> for high cutoff frequencies of bipolar and MOS transistors without degradation of leakage currents. In result, a 300°C/450°C silicidation is proposed providing R<jats:sub>S</jats:sub> values of 3 to 4 Ω for both NiSi and NiPtSi. However, only the NiPtSi shows acceptable low leakage currents compared to NiSi. Therefore, NiPt extends the silicide process window for HBTs and MOSFETs.</jats:p> <jats:p>The phase transitions of Ni and NiPt silicides as a function of temperature are shown in Fig. 1, where the temperature range of the targeted NiSi phase is enlarged for NiPt compared to Ni. The investigated two-step NiSi formations are listed in Table 1. The NiPt layers were deposited in an Applied Materials laboratory. First, Ni<jats:sub>2</jats:sub>Si was formed by furnace anneal, low pressure anneals, or by a NiPt sputtering at 400°C. The Ni rich silicide was converted into NiSi by a second anneal at 450°C.</jats:p> <jats:p>The final Ni(Pt)Si sheet resistance (R<jats:sub>S Ni(Pt)Si:1.+2.Ann</jats:sub>) was tunable from 1.5 Ω to 10.5 Ω by the temperature and time of the first anneal (Fig. 2). At 300°C, the R<jats:sub>S</jats:sub> saturates at 3.3 Ω for 20 nm Ni and 1.6 Ω for 40 nm Ni, respectively. This indicates full Ni consumption. The furnace anneals at 200°C and 230°C do not show any R<jats:sub>S</jats:sub> saturation since Ni is consumed only partially. An R<jats:sub>S</jats:sub> increase for NiSi and NiPtSi on PSD (p source-drain) compared to NiSi on substrate is observed.</jats:p> <jats:p>One figure of merit of SiGe-HBTs is the maximum oscillation frequency f<jats:sub>max</jats:sub>, which depends by the following equation f<jats:sub>max</jats:sub>=sqrt(f<jats:sub>T</jats:sub>/(8πr<jats:sub>B</jats:sub>c<jats:sub>BC</jats:sub>)) on the transit frequency f<jats:sub>T</jats:sub>, the base resistance r<jats:sub>B</jats:sub>, and the collector-base capacitance c<jats:sub>BC</jats:sub>. A silicide resistance variation could mainly influence r<jats:sub>B</jats:sub>. In Fig. 3a, the sheet resistance of the silicided base polysilicon (R<jats:sub>S BasePolySilicide</jats:sub>) together with f<jats:sub>max</jats:sub> of two HBT layouts are plotted for several silicide formations. It exists a correlation between f<jats:sub>max</jats:sub> and R<jats:sub>S BasePolySilicide</jats:sub>, which is shown in Fig. 3b. In general, f<jats:sub>max</jats:sub> could be enlarged by a silicide resistance reduction for special HBT layouts.</jats:p> <jats:p>For these low-ohmic and thick Ni(Pt)Si layers, special attention has to be paid to the MOSFET leakage currents, which can be enlarged by lateral silicide pipes towards the conducting channel or by defects along the SD – STI (shallow trench isolation) interface [2]. Another leakage current source are silicide spikes shortening in a perpendicular direction the SD and the well. Three types of P<jats:sup>+</jats:sup>Nwell and N<jats:sup>+</jats:sup>Pwell diodes are suitable to determine and distinguish these silicide based yield killers: area diodes to detect spikes, STI separated island diodes to recognize SD-STI defects, and diodes with long poly-gates on SD-well areas to determine pipes at gate edges. In result, the area and island diodes showed no leakage current increase for the studied silicidations, i.e. defects along the SD-STI edge and spikes are not critical here. The leakage currents of gate-edged diodes on N<jats:sup>+</jats:sup>Pwell and P<jats:sup>+</jats:sup>Nwell are presented in Fig.4. Both diode types show low leakage currents for the 200°C and 230°C anneals, because the low lateral silicidation at these temperatures reduces the probability for piping. At 300° the N<jats:sup>+</jats:sup>Pwell leakage current increases slightly up to 2x10<jats:sup>-9</jats:sup>A, but significantly up to 1x10<jats:sup>-7</jats:sup>A for the P<jats:sup>+</jats:sup>Nwell diode. This is a clear indication for pipes at the gate edges [3]. In contrast, almost no enhanced leakage current was observed for the NiPt silicidations with 200° to 300°C anneals. The pipe suppression of the NiPt silicide system might be caused by the Pt agglomeration at the silicide-SD interface [4]. The limits of the NiPt pipe suppression are shown for N<jats:sup>+</jats:sup>Pwell diodes silicidated with a NiPt deposition at 400°C. Leakage currents of 1x10<jats:sup>-8</jats:sup>A could indicate NMOS-typical pipes, as described by Yamaguchi [5].</jats:p> <jats:p>In summary, silicide layers with low R<jats:sub>S</jats:sub> values of 3Ω to 4Ω were formed by two-step annealing of Ni and NiPt at 300°C and 450°C. These silicides support high f<jats:sub>max</jats:sub> values of SiGe HBTs. However, only the NiPt silicide process provided acceptable low leakage currents of MOSFET test structures indicating an extended process capability of NiPtSi compared to NiSi.</jats:p> <jats:p> <jats:inline-formula> <jats:inline-graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="1749fig1.jpg" xlink:type="simple" /> </jats:inline-formula> </jats:p> <jats:p>Figure 1</jats:p> <jats:p />
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