Efficiently Testable Circuits

Medientyp: Elektronischer Konferenzbericht; E-Artikel; Sonstige Veröffentlichung

Titel: Efficiently Testable Circuits

Beteiligte: Baig, Mirza Ahad [VerfasserIn]; Chakraborty, Suvradip [VerfasserIn]; Dziembowski, Stefan [VerfasserIn]; Gałązka, Małgorzata [VerfasserIn]; Lizurej, Tomasz [VerfasserIn]; Pietrzak, Krzysztof [VerfasserIn]

Erschienen: Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2023

Sprache: Englisch

DOI: https://doi.org/10.4230/LIPIcs.ITCS.2023.10

Schlagwörter: circuit integrity ; circuit testing ; circuit compilers

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Beschreibung: In this work, we put forward the notion of "efficiently testable circuits" and provide circuit compilers that transform any circuit into an efficiently testable one. Informally, a circuit is testable if one can detect tampering with the circuit by evaluating it on a small number of inputs from some test set. Our technical contribution is a compiler that transforms any circuit C into a testable circuit (Ĉ,𝕋̂) for which we can detect arbitrary tampering with all wires in Ĉ. The notion of a testable circuit is weaker or incomparable to existing notions of tamper-resilience, which aim to detect or even correct for errors introduced by tampering during every query, but our new notion is interesting in several settings, and we achieve security against much more general tampering classes - like tampering with all wires - with very modest overhead. Concretely, starting from a circuit C of size n and depth d, for any L (think of L as a small constant, say L = 4), we get a testable (Ĉ,𝕋̂) where Ĉ is of size ≈ 12n and depth d+log(n)+L⋅ n^{1/L}. The test set 𝕋̂ is of size 4⋅ 2^L. The number of extra input and output wires (i.e., pins) we need to add for the testing is 3+L and 2^L, respectively.

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