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Abdelhalim, Shorouk [VerfasserIn]; Germchi, Danesh [VerfasserIn]; Hossam, Mohamed [VerfasserIn]; Pellizzoni, Rodolfo [VerfasserIn]; Hassan, Mohamed [VerfasserIn] ; Shorouk Abdelhalim and Danesh Germchi and Mohamed Hossam and Rodolfo Pellizzoni and Mohamed Hassan [MitwirkendeR]

A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources

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  • Medientyp: Elektronischer Konferenzbericht; Sonstige Veröffentlichung; E-Artikel
  • Titel: A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources
  • Beteiligte: Abdelhalim, Shorouk [VerfasserIn]; Germchi, Danesh [VerfasserIn]; Hossam, Mohamed [VerfasserIn]; Pellizzoni, Rodolfo [VerfasserIn]; Hassan, Mohamed [VerfasserIn]
  • Erschienen: Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2023
  • Sprache: Englisch
  • DOI: https://doi.org/10.4230/LIPIcs.ECRTS.2023.17
  • Schlagwörter: Main Memory ; Predictability ; Caches ; Real-time
  • Entstehung:
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  • Beschreibung: To facilitate the safe adoption of multi-core platforms in real-time systems, a plethora of recent research efforts aim at bounding the delays induced by interference upon accessing the shared memory resources in these platforms. These efforts, despite their value, are scattered, with each one focusing solely on only one of these resources with the premise that latency bounds separately driven for each resource can be added all together to provide a safe end-to-end memory bound. In this work, we put this assumption to the test for the first time by 1) considering a realistic multi-core memory hierarchy system, 2) deriving the bounds for accessing the shared resources in this system, and 3) highlighting the limitations of this widely-adopted approach. In particular, we show that this approach leads to not only excessively pessimistic but also unsafe bounds. Motivated by these findings, we propose GRROF: a novel approach to predictably and efficiently schedule memory requests while traversing the entire memory hierarchy through coordination among arbiters managing all the resources in this hierarchy. By virtue of this novel mechanism, we managed to exploit pipelining upon analyzing the latency of the memory requests for tightly bounding the worst-case latency. We prove in the paper that GRROF enables us to derive a drastically tighter bound compared to the common additive latency approach with more than 18× reduction in the end-to-end memory latency bound for a modern Out-of-Order quad-core platform. The reduction is further improved significantly with the increase in the number of cores. The proposed solution is fully prototyped and tested in a cycle-accurate simulation. We also compare it with real-time competitive state-of-the-art and performance-oriented solutions existing in modern Commercial-off-the-Shelf (COTS) platforms.
  • Zugangsstatus: Freier Zugang