Beschreibung:
<jats:title>Abstract</jats:title>
<jats:p>In this article an 8-bit differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), designed in the 28 nm CMOS process is presented. It is aimed at pixelated radiation imaging detectors. It allows to distinguish 256 levels of energy and is capable of converting 10 MS/s. The measured INL and DNL are ±0.5 LSB and ±0.3 LSB, respectively. Importantly, the proposed ADC’s comparator offset voltage correction is realized in a time domain allowing to shift the transfer characteristics within the 12 LSB range with no conversion rate degradation. The core of the ADC occupies only 30 µm × 60 µm and the power consumption is 45 µW.</jats:p>