• Medientyp: E-Artikel
  • Titel: Verilog HDL and its ancestors and descendants
  • Beteiligte: Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon
  • Erschienen: Association for Computing Machinery (ACM), 2020
  • Erschienen in: Proceedings of the ACM on Programming Languages
  • Sprache: Englisch
  • DOI: 10.1145/3386337
  • ISSN: 2475-1421
  • Schlagwörter: Safety, Risk, Reliability and Quality ; Software
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  • Beschreibung: <jats:p>This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.</jats:p>
  • Zugangsstatus: Freier Zugang