Beschreibung:
<jats:p>On-chip clock networks are remarkable in their
impact on the performance and power of synchronous circuits, in
their susceptibility to adverse effects of semiconductor technology
scaling, as well as in their strong potential for improvement
through better CAD algorithms and tools. Existing literature
is rich in ideas and techniques but performs large-scale optimization
using analytical models that lost accuracy at recent
technology nodes and have rarely been validated by realistic
SPICE simulations <jats:italic>on large industry designs</jats:italic>.
Our work offers a methodology for SPICE-accurate optimization
of clock networks, coordinated to satisfy slew constraints
and achieve best tradeoffs between skew, insertion delay, power,
as well as tolerance to variations. Our implementation, called
Contango, is evaluated on 45 nm benchmarks from IBM Research
and Texas Instruments with up to 50 K sinks. It outperforms all
published results in terms of skew and shows superior scalability.</jats:p>