Erschienen:
National Aerospace University - Kharkiv Aviation Institute, 2023
Erschienen in:
Radioelectronic and Computer Systems (2023) 2, Seite 94-106
Sprache:
Ohne Angabe
DOI:
10.32620/reks.2023.2.08
ISSN:
2663-2012;
1814-4225
Entstehung:
Anmerkungen:
Beschreibung:
The work is devoted to the topical problem at the intersection of communications theory, digital electronics and numerical analysis, namely the study of image processing methods implementation time on different architectures of computational devices, which are used for software and hardware acceleration. The subject of this article is the investigation of reconfigurable FPGA processing systems in the image processing area. The goal of this work is to create a reconfigurable FPGA-based image processing system and compare it with existing processing architectures. Task. To fulfill the requirements of this work, it is necessary to prepare a practical experiment as well as theoretical research of the proposed architecture; to investigate the process of creating a ZYNQ SoC-based image processing system; and to develop and benchmark the speed of execution for the given set of algorithms with the specific range of the picture resolution. Methods used: FPGA simulation, C++ parallel programming with OpenMP, NVIDIA CUDA, performance analysis tools. The result of this work is the development of a resilient SoC Zynq7000–based computing system with programmable logic and the possibility to load images to FPGA RAM using the resources of ARM core for further processing and output via HDMI video interface, which enables the change of PL configuration at any time during the processing process. Conclusions. The efficiency of the FPGA approach was compared with a parallel image processing method implementation with OpenMP and CUDA. An overview of the ZYNQ platform with specific details related to media processing is presented. The analysis of algorithm speed testing findings based on various outputs proved the advantage (of over 60 times) of hardware acceleration of image processing over software analogs. The obtained results may be used in the development of embedded SoC-based solutions that require acceleration of big data processing. Also, the achieved findings can be used during the process of finding a suitable embedded platform for a certain image-processing task, where high data throughput is one of the most desired requirements.