Media type: E-Article Title: A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise Contributor: Bindra, Harijot Singh; Lokin, Christiaan E.; Schinkel, Daniel; Annema, Anne-Johan; Nauta, Bram imprint: Institute of Electrical and Electronics Engineers (IEEE), 2018 Published in: IEEE Journal of Solid-State Circuits Language: Not determined DOI: 10.1109/jssc.2018.2820147 ISSN: 0018-9200; 1558-173X Keywords: Electrical and Electronic Engineering Origination: Footnote: