Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

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Titel: Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Beteiligte: Schoeberl, Martin [Verfasser:in]; Schleuniger, Pascal [Verfasser:in]; Puffitsch, Wolfgang [Verfasser:in]; Brandner, Florian [Verfasser:in]; Probst, Christian W. [Verfasser:in]

Erschienen: Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2011

Sprache: Englisch

DOI: https://doi.org/10.4230/OASIcs.PPES.2011.11

Schlagwörter: WCET analysis ; WCET-aware compilation ; Time-predictable architecture

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Beschreibung: Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual-issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.

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